This invention relates generally to a voltage controlled oscillator (VCO) circuit adapted for use in digital processing of video, audio or other such signals.
Reference is made to FIG. 1 which shows a block diagram of an arrangement for a conventional sampling clock generating phase locked loop (PLL) circuit which generates horizontal sampling clocks of a video signal. A horizontal sync signal 24 is provided at the input of the circuit as a reference signal for phase comparator (PC) 20. The frequency of the signal at the output 26 of voltage controlled oscillator (VCO) 22 is divided at N frequency divider 23 and placed on line 25 which is an input to phase comparator or detector 20. The horizontal sync signal 24 is compared with divided signal 25 in comparator 20 to produce a phase compensation value, which is then converted into a DC voltage component in low pass filter (LPF) 21. This DC component is feed back to VCO 22 to maintain its output in phase with reference signal 24 thereby producing an output frequency signal 26 from VCO 22 in phase with input frequency signal 24 having desired sampling clock characteristics. However, this PLL circuit does not effectively lock to the input reference signal particularly relative to applications where the horizontal sync signal contain inferior phase stability such as in laser disc apparatus, video tape apparatus, other such mechanical video devices, such as a laser disc player or a video tape deck, or the like and digital video processing circuits and the like. As a result, the sampling clock signal at output 24 is not continually maintained or stabilized in phase with input sync signal and there results an unsteadiness in the displayed picture commonly referred to as "jitter". In other words, technically, jitter is the fluctuation or change in the active sync pulse width so that the overall phase relation among a group of sync pulses, for example, is not uniform.
It is an object of the present invention to provide a VCO that is capable of an output of a sampling clock signal synchronized with a horizontal sync signal even if the stability in phase of the horizontal sync signal is not good and, further, enables the sampling clock frequency to be readily changed without narrowing the variable frequency range of the PLL circuit.